 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| IDT23S08T 2.5V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL TEMPERATURE RANGE 2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE FEATURES: DESCRIPTION: IDT23S08T ADVANCE INFORMATION * Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency * Distributes one clock input to two banks of four outputs * Separate output enable for each output bank * External feedback (FBK) pin is used to synchronize the outputs to the clock input * Output Skew <200 ps * Low jitter <200 ps cycle-to-cycle * 1/2x, 1x, 2x, 4x output options (see table): - IDT23S08T-1 1x - IDT23S08T-2 1x, 2x - IDT23S08T-3 2x, 4x - IDT23S08T-4 2x - IDT23S08T-5 1/2x * No external RC network required * Operates at 2.5V VDD * Spread spectrum compatible * Available in SOIC package The IDT23S08T is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT23S08T has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the IDT23S08T enters power down. In this mode, the device will draw less than 12A, and the outputs are tri-stated. The IDT23S08T is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.) The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The IDT23S08T is characterized for Commercial operation. FUNCTIONAL BLOCK DIAGRAM (-3, -4) FBK REF 16 1 2 (-5) 3 CLKA2 2 PLL 2 CLKA1 14 CLKA3 15 CLKA4 S2 S1 8 9 Control Logic (-2, -3) 2 6 CLKB1 7 CLKB2 10 CLKB3 11 CLKB4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1 c 2003 Integrated Device Technology, Inc. NOVEMBER 2003 DSC - 6510/4 IDT23S08T 2.5V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD Rating Supply Voltage Range Input Voltage Range (REF) Input Voltage Range (except REF) IIK (VI < 0) IO (VO = 0 to VDD) VDD or GND TA = 55C (in still air)(3) TSTG Operating Temperature Storage Temperature Range Commercial Temperature Range -65 to +150 0 to +70 C C Continuous Current Maximum Power Dissipation 100 0.7 mA W Input Clamp Current Continuous Output Current Max. -0.5 to +4.6 -0.5 to +5.5 -0.5 to VDD+0.5 -50 50 mA mA Unit V V V VI (2) VI REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 SOIC TOP VIEW NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. PIN DESCRIPTION Pin Number REF (1) Functional Description Input Reference Clock, 3.3V Tolerant Input Clock Output for Bank A Clock Output for Bank A 2.5V Supply Ground Clock Output for Bank B Clock Output for Bank B Select Input, Bit 2 Select Input, Bit 1 Clock Output for Bank B Clock Output for Bank B Ground 2.5V Supply Clock Output for Bank A Clock Output for Bank A PLL Feedback Input 1 2 3 4 5 CLKA1(2) CLKA2 VDD GND CLKB1 S2(3) S1(3) CLKB3 CLKB4 GND VDD CLKA3(2) CLKA4(2) FBK (2) (2) (2) (2) 6 7 8 9 10 11 12 13 14 15 16 CLKB2(2) APPLICATIONS: * * * * * SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs NOTES: 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull ups on these inputs. 2 IDT23S08T 2.5V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL TEMPERATURE RANGE FUNCTION TABLE(1) SELECT INPUT DECODING S2 L L H H NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level S1 L H L H CLK A Tri-State Driven Driven Driven CLK B Tri-State Tri-State Driven Driven Output Source PLL PLL REF PLL PLL Shut Down Y N Y N AVAILABLE OPTIONS FOR IDT23S08T Device IDT23S08T-1 IDT23S08T-2(1) IDT23S08T-2(1) IDT23S08T-3(1) IDT23S08T-3(1) IDT23S08T-4 (1) Feedback From Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference 2 x Reference 2 x Reference 4 x Reference 2 x Reference Reference/2 Bank B Frequency Reference Reference/2 Reference Reference or Reference(2) 2 x Reference 2 x Reference Reference/2 IDT23S08T-5(1) NOTES: 1. Contact factory for availability. 2. Output phase is indeterminant (0 or 180 from input clock). SPREAD SPECTRUM COMPATIBLE Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization. ZERO DELAY AND SKEW CONTROL To close the feedback loop of the IDT23S08T, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are loaded equally, for zero output-output skew. OPERATING CONDITIONS Symbol VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance from 10MHz to 133MHz Input Capacitance(1) Parameter Test Conditions Min. 2.3 0 -- -- Max. 2.7 70 15 7 Unit V C pF pF NOTE: 1. Applies to both REF and FBK. 3 IDT23S08T 2.5V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS Symbol VIL VIH IIL IIH VOL VOH IDD_PD IDD Parameter Input LOW Voltage Level Input HIGH Voltage Level Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Power Down Current Supply Current VIN = 0V VIN = VDD IOL = 8mA IOH = -8mA REF = 0MHz (S2 = S1 = H) 100MHz CLKA Unloaded Outputs Select Inputs at VDD or GND 66MHz CLKA 33MHz CLKA Conditions Min. -- 1.7 -- -- -- 2 -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -- -- Max. 0.7 -- 50 100 0.3 -- 12 45 32 18 mA Unit V V A A V V A SWITCHING CHARACTERISTICS Symbol t1 t3 t4 t5 Parameter Output Frequency Duty Cycle = t2 / t1 Rise Time Fall Time Output to Output Skew on same Bank (-1, -2, -3, -4, -5) Output Bank A to Output Bank B (-1, -4, -5) Output Bank A to Output Bank B Skew (-2, -3) t6 t7 tJ tJ Conditions 15pF Load Measured at VDD/2, FOUT = 66.66MHz, 15pF Load Measured between 0.7V and 1.7V, 15pF Load Measured between 0.7V and 1.7V, 15pF Load All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured at 66.67 MHz, loaded outputs, 15pF Load Measured at 133.3 MHz, loaded outputs, 15pF Load Measured at 66.67 MHz, loaded outputs, 15pF Load Stable Power Supply, valid clocks presented on REF and FBK pins Min. 10 40 -- -- -- -- -- -- -- -- -- -- -- Typ. -- 50 -- -- -- -- -- 0 0 -- -- -- -- Max. 133.3 60 2.5 2.5 200 200 400 350 700 200 200 400 1 Unit MHz % ns ns ps ps ps ps ps ps ps ms Delay, REF Rising Edge to FBK Rising Edge Device to Device Skew Cycle to Cycle Jitter (-1, -4, -5) Cycle to Cycle Jitter (-2, -3) PLL Lock Time tLOCK 4 IDT23S08T 2.5V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL TEMPERATURE RANGE SWITCHING WAVEFORMS t1 t2 VDD/2 VDD/2 VDD/2 Duty Cycle Timing Output 0.7V t3 1.7V 1.7V 0.7V t4 2.5V 0V All Outputs Rise/Fall Time VDD/2 Output VDD/2 t5 Output to Output Skew VDD/2 Input FBK t6 Input to Output Propagation Delay Output VDD/2 VDD/2 FBK, Device 1 FBK, Device 2 t7 VDD/2 TEST CIRCUIT VDD 0.1F OUTPUTS CLKOUT CLOAD Device to Device Skew VDD 0.1F GND GND Test Circuit for all Parameters 5 IDT23S08T 2.5V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type XX Package X Process Blank Commercial (0oC to +70oC) DC 23S08T-1 23S08T-2 23S08T-3 23S08T-4 23S08T-5 Small Outline 2.5V Zero Delay Clock Buffer, Spread Spectrum Compatible Ordering Code IDT23S08T-1DC IDT23S08T-2DC(1) IDT23S08T-3DC(1) IDT23S08T-4DC(1) IDT23S08T-5DC (1) Package Type 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC Commercial Commercial Commercial Commercial Commercial Operating Range NOTE: 1. Contact factory for availability. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: logichelp@idt.com (408) 654-6459 |
Price & Availability of IDT23S08T-1
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |